Throughout the evolution of integrated circuits, the aim of device scaling has been to increase circuit performance and to increase the functional complexity of the circuits. At the outset, scaling down of active device sizes was a very effective means of achieving these goals. Commonly, the functional complexity of the circuits in shrinking dimensions are limited by the characteristics of the metallic conductors (commonly referred to as interconnects) that provide the electrical connections between the underlying elements. The key characteristics considered when employing such interconnects are the minimum width and separation of the conductor features as well as the total number of interconnect levels that are required.
In order, to satisfactorily use interconnects with the required small dimensions, the surface of the integrated circuit must maintain a required degree of planarization throughout the fabrication process. Such planarization is required because of the demands of high resolution photolithography processes used during fabrication. While employing the photolithographic process, the printing of higher resolution features comes at the expense of decreased focus depths. The surface must maintain a high enough degree of planarization so that features in every area of a chip may be printed in focus. Failure to maintain this degree of planarity will result in device yield loss due to irregularities in the interconnect layers.
The non-planarity of the top surface of a integrated circuit is determined by the cumulative non-planarity of all the underlying levels. Therefore, as the number of underlying interconnect levels is increased, the degree of planarization of each level must be increased in order to maintain the required planarity at the uppermost level. For a more thorough discussion of planarization and the effects of non-planarity on photolithography, see S. Wolf's, Silicon Processing for the VLSI Era, Vol. 2, which is incorporated herein by reference.
The term planarization is generally well known to those skilled in the art. Those skilled in the art are also familiar with the fact that there are varying degrees of planarization. A planarized surface, as used herein, shall mean a substantially planar surface, that is, it is a surface where typically the difference between the highest and lowest points has been reduced to less than 15% of the initial value after a planarizing process, rather than absolutely planar. Such planarization may be implemented in either the conductor or the dielectric layers. Without such planarization, the microscopic recessed areas that result on the wafer surface from the stacking of device features can lead to topography conditions that would eventually reduce the yield of circuits to unacceptably small values.
Distinction is also often made between a locally planarized surface and a globally planarized surface. A locally planarized surface is characterized by the absence of large recesses or protrusions in the surface. The surface is flat over short distances but not necessarily over long distances. A locally planarized surface can have long gentle slopes such that an appreciable height difference can occur over the several millimeter length of an integrated circuit. In contrast, a globally planarized surface is flat over dimensions greater than that of single large integrated circuits.
Currently, the most commonly used planarization technique used for fabricating integrated circuit is chemical mechanical polishing (CMP). CMP removes material from the wafer surface through a combination of chemical etching and mechanical abrasion of the dielectric layer. CMP at a dielectric level preferentially removes the high portions of the uppermost dielectric layer, which occur in areas directly above underlying interconnect topography.
Many problems arise, however, when a CMP process is employed for wafer planarization. Significant deviation from global planarity often results due to pattern density effects. The dielectric removal rate during CMP is lower for regions with a high density of underlying interconnect structures because a large fraction of the wafer surface contacts the polishing pad in these regions. Consequently, the height of the dielectric layer will vary dramatically across the chip depending on the underlying metal pattern density.
Additionally, CMP processes often result in severe wafer to wafer variations in dielectric thickness due to systematic changes in CMP polish rate with number of wafers polished. Consequently, the CMP process must be closely monitored throughout the production and customized each time a different device is produced. This results in high production costs and lost time as the fabrication equipment must be re-calibrated with each successive lot of wafers.
Employing a CMP process also commonly results in significant lot to lot variability of the remaining oxide. Different types of integrated circuit devices will possess different metal pattern densities. Both the absolute metal pattern density and its distribution across the chip area can vary significantly between devices. These effects require the CMP process to be closely monitored throughout the production and customized each time a different device is produced. This monitoring results in high production costs and lost time as the fabrication equipment must be re-calibrated with each successive lot of wafers.
Accordingly, what is needed in the art is a method for planarizing an irregular surface of a semiconductor wafer that avoids the problems associated with prior art methods.